SIC/XE Reference

Instructions

The below table is copied from Appendix A of System Software: An Introduction to Systems Programming . Note that for format 3/4 instructions, the opcode is really 6 bits. The last two bits are used for bits n and i.

Notes

  • P: Privileged instruction
  • X: Instruction available only on SIC/XE
  • F: Floating-point instruction
  • C: Condition code (CC) set to indicate the result of the operation (<, =, or >)
MnemonicFormatOpcodeEffectNotes
ADD m3/418 = 0001 1000A ← (A) + (m..m+2)
ADDF m3/458 = 0101 1000F ← (F) + (m..m+5)X F
ADDR r1,r2290 = 1001 0000r2 ← (r2) + (r1)X
AND m3/440 = 0100 0000A ← (A) & (m..m+2)
CLEAR r12B4 = 1011 0100r1 ← 0X
COMP m3/428 = 0010 1000(A) : (m..m+2)C
COMPF m3/488 = 1000 1000(F) : (m..m+5)X F C
COMPR r1,r22A0 = 1010 0000(r1) : (r2)X C
DIV m3/424 = 0010 0100A ← (A) / (m..m+2)
DIVF m3/464 = 0110 0100F ← (F) / (m..m+5)X F
DIVR r1,r229C = 1001 1100r2 ← (r2) / (r1)X
FIX1C4 = 1100 0100A ← (F) [convert to integer]X F
FLOAT1C0 = 1100 0000F ← (A) [convert to floating]X F
HIO1F4 = 1111 0100Halt I/O channel number (A)P X
J m3/43C = 0011 1100PC ← m
JEQ m3/430 = 0011 0000PC ← m if CC set to =
JGT m3/434 = 0011 0100PC ← m if CC set to >
JLT m3/438 = 0011 1000PC ← m if CC set to <
JSUB m3/448 = 0100 1000L ← (PC); PC ← m
LDA m3/400 = 0000 0000A ← (m..m+2)
LDB m3/468 = 0110 1000B ← (m..m+2)X
LDCH m3/450 = 0101 0000A [rightmost byte] ← (m)
LDF m3/470 = 0111 0000F ← (m..m+5)X F
LDL m3/408 = 0000 1000L ← (m..m+2)
LDS m3/46C = 0110 1100S ← (m..m+2)X
LDT m3/474 = 0111 0100T ← (m..m+2)X
LDX m3/404 = 0000 0100X ← (m..m+2)
LPS m3/4D0 = 1101 0000Load processor status from information beginning at address mP X
MUL m3/420 = 0010 0000A ← (A) * (m..m+2)
MULF m3/460 = 0110 0000F ← (F) * (m..m+5)X F
MULR r1,r2298 = 1001 1000r2 ← (r2) * (r1)X
NORM1C8 = 1100 1000F ← (F) [normalized]X F
OR m3/444 = 0100 0100A ← (A) | (m..m+2)
RD m3/4D8 = 1101 1000A [rightmost byte] ← data from device specified by (m)P
RMO r1,r22AC = 1010 1100r2 ← (r1)X
RSUB3/44C = 0100 1100PC ← (L)
SHIFTL r1,n2A4 = 1010 0100r1 ← (r1); left circular shift n bits.
[In assembled instruction, r2 = n-1]
X
SHIFTR r1,n2A8 = 1010 1000r1 ← (r1);
right shift n bits, with vacated bit positions set equal to leftmost bit of (r1).
[In assembled instruction, r2 = n-1]
X
SIO1F0 = 1111 0000Start I/O channel number (A); address of channel program is given by (S)P X
SSK m3/4EC = 1110 1100Protection key for address m ← (A)P X
STA m3/40C = 0000 1100m..m+2 ← (A)
STB m3/478 = 0111 1000m..m+2 ← (B)X
STCH m3/454 = 0101 0100m ← (A) [rightmost byte]
STF m3/480 = 1000 0000m..m+5 ← (F)X F
STI m3/4D4 = 1101 0100Interval timer value ← (m..m+2)P X
STL m3/414 = 0001 0100m..m+2 ← (L)
STS m3/47C = 0111 1100m..m+2 ← (S)X
STSW m3/4E8 = 1110 1000m..m+2 ← (SW)P
STT m3/484 = 1000 0100m..m+2 ← (T)X
STX m3/410 = 0001 0000m..m+2 ← (X)
SUB m3/41C = 0001 1100A ← (A) - (m..m+2)
SUBF m3/45C = 0101 1100F ← (F) - (m..m+5)X F
SUBR r1,r2294 = 1001 0100r2 ← (r2) - (r1)X
SVC n2B0 = 1011 0000Generate SVC interrupt.
[In assembled instruction, r1 = n]
X
TD m3/4E0 = 1110 0000Test device specified by (m)P C
TIO1F8 = 1111 1000Test I/O channel number (A)P X C
TIX m3/42C = 0010 1100X ← (X) + 1; (X) : (m..m+2)X C
TIXR r12B8 = 1011 1000X ← (X) + 1; (X) : (r1)X C
WD m3/4DC = 1101 1100Device specified by (m) ← (A) [rightmost byte]P

List of Instructions

ADD m

Adds register A and the word at the address m, storing the result in register A.

ADDF m

Floating-point equivalent of ADD. The floating-point number stored at m (6 bytes or 2 words) is added to the value in register F and the result is stored in register F.

ADDR r1,r2

Adds the values of r1 and r2 together, storing the result in r2.

AND m

Performs bitwise AND on register A and the word at m. The result is stored in register A.

CLEAR r1

Sets register r1 to zero, effectively clearing it.

COMP m

Compares of register A to the word at m, setting the condition code.

COMPF m

Floating-point equivalent of COMP. The floating-point number stored at m (6 bytes or 2 words) is compared to the value in register F and the condition code is set.

COMPR r1,r2

Compares the values of r1 and r2, setting the condition code.

DIV m

Divides the value in A by the word at address m. The result is wrote back to register A.

DIVF m

Divides the value in F by the 2 words at address m. The result is wrote back to register F.

DIVR r1,r2

Divides the value of r2 by r1, storing the result in r2.

FIX

Reads the float in F, converts it to an integer, and stores it in A.

FLOAT

Reads the integer in A, converts it to a floating-point number, and stores it in F.

HIO

TODO

J m

Jumps to address m by updating the PC register.

JEQ m

Jumps to address m by updating the PC register only if the condition code is set to =.

JGT m

Jumps to address m by updating the PC register only if the condition code is set to >.

JLT m

Jumps to address m by updating the PC register only if the condition code is set to <.

JSUB m

Sets the L register to the current value of PC and then jumps to address m by setting PC.

LDA m

Loads the word at address m into the A register.

LDB m

Loads the word at address m into the B register.

LDCH m

Loads the byte at address m into the right-most byte of the A register.

LDF m

Loads two words at address m into the F register.

LDL m

Loads the word at address m into the L register.

LDS m

Loads the word at address m into the S register.

LDT m

Loads the word at address m into the T register.

LDX m

Loads the word at address m into the X register.

LPS m

TODO

MUL m

TODO

MULF m

TODO

MULR r1,r2

TODO

NORM

Normalizes the float in the F register.

OR m

Performs bitwise OR on the word at address m and the word in register A, storing the result in register A.

RD m

TODO

RMO r1,r2

Copies the value in register r1 into register r2.

RSUB

Returns from a subroutine by reading the value of L (set by JSUB) and setting PC to it, jumping back to where JSUB was called.

SHIFTL r1,n

TODO

SHIFTR r1,n

TODO

SIO

TODO

SSK m

TODO

STA m

TODO

STB m

TODO

STCH m

TODO

STF m

TODO

STI m

TODO

STL m

TODO

STS m

TODO

STSW m

TODO

STT m

TODO

STX m

TODO

SUB m

TODO

SUBF m

TODO

SUBR r1,r2

TODO

SVC n

TODO

TD m

TODO

TIO

TODO

TIX m

TODO

TIXR r1

TODO

WD m

TODO

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