Instructions
The below table is copied from Appendix A of System Software: An Introduction to Systems Programming. Note that for format 3/4 instructions, the opcode is really 6 bits. The last two bits are used for bits n and i.
Notes
P: Privileged instruction
X: Instruction available only on SIC/XE
F: Floating-point instruction
C: Condition code (CC) set to indicate the result of the operation (<, =, or >)
Mnemonic | Opcode | Effect | Notes | |
|---|---|---|---|---|
3/4 |
| A ← (A) + (m..m+2) | ||
3/4 |
| F ← (F) + (m..m+5) | X F | |
2 |
| r2 ← (r2) + (r1) | X | |
3/4 |
| A ← (A) & (m..m+2) | ||
2 |
| r1 ← 0 | X | |
3/4 |
| (A) : (m..m+2) | C | |
3/4 |
| (F) : (m..m+5) | X F C | |
2 |
| (r1) : (r2) | X C | |
3/4 |
| A ← (A) / (m..m+2) | ||
3/4 |
| F ← (F) / (m..m+5) | X F | |
2 |
| r2 ← (r2) / (r1) | X | |
1 |
| A ← (F) [convert to integer] | X F | |
1 |
| F ← (A) [convert to floating] | X F | |
1 |
| Halt I/O channel number (A) | P X | |
3/4 |
| PC ← m | ||
3/4 |
| PC ← m if CC set to = | ||
3/4 |
| PC ← m if CC set to > | ||
3/4 |
| PC ← m if CC set to < | ||
3/4 |
| L ← (PC); PC ← m | ||
3/4 |
| A ← (m..m+2) | ||
3/4 |
| B ← (m..m+2) | X | |
3/4 |
| A [rightmost byte] ← (m) | ||
3/4 |
| F ← (m..m+5) | X F | |
3/4 |
| L ← (m..m+2) | ||
3/4 |
| S ← (m..m+2) | X | |
3/4 |
| T ← (m..m+2) | X | |
3/4 |
| X ← (m..m+2) | ||
3/4 |
| Load processor status from information beginning at address m | P X | |
3/4 |
| A ← (A) * (m..m+2) | ||
3/4 |
| F ← (F) * (m..m+5) | X F | |
2 |
| r2 ← (r2) * (r1) | X | |
1 |
| F ← (F) [normalized] | X F | |
3/4 |
| A ← (A) | (m..m+2) | ||
3/4 |
| A [rightmost byte] ← data from device specified by (m) | P | |
2 |
| r2 ← (r1) | X | |
3/4 |
| PC ← (L) | ||
2 |
| r1 ← (r1); left circular shift n bits. | X | |
2 |
| r1 ← (r1); | X | |
1 |
| Start I/O channel number (A); address of channel program is given by (S) | P X | |
3/4 |
| Protection key for address m ← (A) | P X | |
3/4 |
| m..m+2 ← (A) | ||
3/4 |
| m..m+2 ← (B) | X | |
3/4 |
| m ← (A) [rightmost byte] | ||
3/4 |
| m..m+5 ← (F) | X F | |
3/4 |
| Interval timer value ← (m..m+2) | P X | |
3/4 |
| m..m+2 ← (L) | ||
3/4 |
| m..m+2 ← (S) | X | |
3/4 |
| m..m+2 ← (SW) | P | |
3/4 |
| m..m+2 ← (T) | X | |
3/4 |
| m..m+2 ← (X) | ||
3/4 |
| A ← (A) - (m..m+2) | ||
3/4 |
| F ← (F) - (m..m+5) | X F | |
2 |
| r2 ← (r2) - (r1) | X | |
2 |
| Generate SVC interrupt. | X | |
3/4 |
| Test device specified by (m) | P C | |
1 |
| Test I/O channel number (A) | P X C | |
3/4 |
| X ← (X) + 1; (X) : (m..m+2) | X C | |
2 |
| X ← (X) + 1; (X) : (r1) | X C | |
3/4 |
| Device specified by (m) ← (A) [rightmost byte] | P |
List of Instructions
ADD m
Adds register A and the word at the address m, storing the result in register A.
ADDF m
Floating-point equivalent of ADD. The floating-point number stored at m (6 bytes or 2 words) is added to the value in register F and the result is stored in register F.
ADDR r1,r2
Adds the values of r1 and r2 together, storing the result in r2.
AND m
Performs bitwise AND on register A and the word at m. The result is stored in register A.
CLEAR r1
Sets register r1 to zero, effectively clearing it.
COMP m
Compares of register A to the word at m, setting the condition code.
COMPF m
Floating-point equivalent of COMP. The floating-point number stored at m (6 bytes or 2 words) is compared to the value in register F and the condition code is set.
COMPR r1,r2
Compares the values of r1 and r2, setting the condition code.
DIV m
Divides the value in A by the word at address m. The result is wrote back to register A.
DIVF m
Divides the value in F by the 2 words at address m. The result is wrote back to register F.
DIVR r1,r2
Divides the value of r2 by r1, storing the result in r2.
FIX
Reads the float in F, converts it to an integer, and stores it in A.
FLOAT
Reads the integer in A, converts it to a floating-point number, and stores it in F.
HIO
TODO
J m
Jumps to address m by updating the PC register.
JEQ m
Jumps to address m by updating the PC register only if the condition code is set to =.
JGT m
Jumps to address m by updating the PC register only if the condition code is set to >.
JLT m
Jumps to address m by updating the PC register only if the condition code is set to <.
JSUB m
Sets the L register to the current value of PC and then jumps to address m by setting PC.
LDA m
Loads the word at address m into the A register.
LDB m
Loads the word at address m into the B register.
LDCH m
Loads the byte at address m into the right-most byte of the A register.
LDF m
Loads two words at address m into the F register.
LDL m
Loads the word at address m into the L register.
LDS m
Loads the word at address m into the S register.
LDT m
Loads the word at address m into the T register.
LDX m
Loads the word at address m into the X register.
LPS m
TODO
MUL m
TODO
MULF m
TODO
MULR r1,r2
TODO
NORM
Normalizes the float in the F register.
OR m
Performs bitwise OR on the word at address m and the word in register A, storing the result in register A.
RD m
TODO
RMO r1,r2
Copies the value in register r1 into register r2.
RSUB
Returns from a subroutine by reading the value of L (set by JSUB) and setting PC to it, jumping back to where JSUB was called.
SHIFTL r1,n
TODO
SHIFTR r1,n
TODO
SIO
TODO
SSK m
TODO
STA m
TODO
STB m
TODO
STCH m
TODO
STF m
TODO
STI m
TODO
STL m
TODO
STS m
TODO
STSW m
TODO
STT m
TODO
STX m
TODO
SUB m
TODO
SUBF m
TODO
SUBR r1,r2
TODO
SVC n
TODO
TD m
TODO
TIO
TODO
TIX m
TODO
TIXR r1
TODO
WD m
TODO